This invention relates to a bus capable of transferring variable length packets (e.g. for POS) at a 10 Gbps rate between two separate cards across a midplane or backplane.
The midplane or backplane (midplane/backplane) has a limited number of physical pins available and signals must pass through two connectors, which potentially could introduce signal integrity issues for high-speed signals.
There is a width vs. speed tradeoff, wherein a slower bus rate is easier and more reliable to implement however it must also be wider, which can be inefficient for short packets.
SQULB (prior art) is a sequenced utopia-3 like bus designed for asynchronous transfer mode (ATM) applications, i.e. fixed sized (56-byte) cells, and as such is not capable of handling variable length packets.
In order to modify SQULB to handle variable length packets, the bus must be made four times wider (four-bytes to sixteen-bytes). This solution is not feasible for the following reasons:                1. The limited number of pins available across the midplane/backplane. There is currently no offering of serializer/deserializer (SERDES) devices capable of handling this bus width. Separate SERDES devices would make it difficult to receive the packet data in the proper order and with minimal signal skew.        2. A sixteen-byte wide bus implies that a single packet could contain up to fifteen empty bytes transferred during the end of packet. This transmission model would be very inefficient and would require a large increase in the operating frequency of the physical bus to maintain a 10 Gbps rate.        